1. Field of the Invention
Embodiments of the present invention generally relate to memory systems and, more specifically, to improvements to such memory systems.
2. Description of the Related Art
Dual inline memory modules (DIMMs) are typically constructed as single-rank, dual-rank, or quad-rank modules, wherein a rank refers to the plurality of memory circuits (e.g. DRAMs) that are controlled by a common control (e.g. chip select) signal and are accessed in parallel by a system that includes a memory controller. These memory modules typically have 64 data bits (i.e. 64-bit wide memory module or memory module with 64-bit wide rank(s)), and optionally may include an additional 8 check bits that provide error detection and correction capability (i.e. 72-bit wide memory module or memory module with 72-bit wide rank(s)).
Standard memory circuits are available with a 16-bit wide data bus (e.g. ×16 DRAM), an 8-bit wide data bus (e.g. ×8 DRAM), or a 4-bit wide data bus (e.g. ×4 DRAM). Consequently, a 72-bit wide memory module requires nine 8-bit wide memory circuits per rank or eighteen 4-bit wide memory circuits per rank. Since memory circuit failures are not an uncommon occurrence, computer architects have developed a technique that allows mission-critical computers to continue operating in the event that a single memory circuit per rank fails. This technique is known by various trademarks such as Chipkill, Advanced ECC, or SDDC (Single Device Data Correction). Modern Chipkill or SDDC requires the use of eighteen memory circuits in parallel to be tolerant to the loss of a single circuit. Memory modules with ×4 memory circuits are typically used in mission-critical servers since they have eighteen memory circuits per rank, and thus provide the server with the ability to continue operating when a single memory circuit per rank has failed.
Memory modules with ×4 memory circuits usually dissipate more power than modules with ×8 memory circuits since eighteen memory circuits respond in parallel to each command from the memory controller whereas only nine memory circuits respond in parallel on modules with ×8 memory circuits. Many server manufacturers choose to offer only memory modules with ×4 memory circuits on some of their server models while choosing to offer memory modules with ×8 memory circuits on other server models. As a result, the end user has less flexibility to select between higher memory reliability and lower memory power.
The different ranks on a memory module share the data bus of the module. For example, in a dual-rank memory module, DQ[3:0] of the module's data bus is connected to the data pins of the memory circuit corresponding to DQ[3:0] of rank 0 and to the data pins of the memory circuit corresponding to DQ[3:0] of rank 1.
Since the ranks on a memory module share the data bus, the memory controller allows for one or more bus turnaround or idle clock cycles between accessing a first rank and accessing a second rank. This turnaround time ensures that there is sufficient time for the memory circuits of the first rank to disconnect from the data bus (e.g. post-amble) and for memory circuits of the second rank to connect to the data bus (e.g. pre-amble). For example, when the memory controller sends a read command to a first rank followed by a read command to a second rank, it ensures that there is at least one clock cycle between the last data from the first rank and the first data from the second rank. This turnaround time creates “bubbles” or idle clock cycles on the shared data bus that interconnects the memory controller and the memory modules, which reduces the utilization of the data bus, which in turn lowers the maximum sustained bandwidth of the memory subsystem.
As the foregoing illustrates, what is needed in the art is a memory subsystem and method that overcome the shortcomings of prior art systems.